Semiconductor memory devices that store data can be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose stored data when power is interrupted, whereas nonvolatile memory devices retain stored data even if the power is abruptly interrupted. Nonvolatile memory devices include flash memory devices. A unit cell of a conventional flash memory device (hereinafter, referred to as a “flash memory cell”) can include an active region defined at a predetermined region of a semiconductor substrate, a tunnel dielectric layer formed on the active region, a floating gate formed on the tunnel dielectric layer, an inter-gate dielectric layer formed on the floating gate, and a control gate electrode formed on the inter-gate dielectric layer.
The flash memory cell may store data while a voltage externally applied to the control gate electrode is being coupled to the floating gate. Thus, in order to store data at a low programming voltage in a short amount of time, a ratio of a voltage induced to the floating gate to the voltage applied to the control gate electrode should be high. The ratio of the voltage induced to the floating gate to the voltage applied to the control gate electrode is termed a “coupling ratio.” The coupling ratio may also be expressed as a ratio of the capacitance of the inter-gate dielectric layer to the sum of the capacitances of the tunnel dielectric layer and the inter-gate dielectric layer.
Meanwhile, as the size of electronic systems using flash memory devices is reduced and the demand for low-power consumption components is increased, a flash memory device should be more highly integrated. To achieve higher integration, a gate for the flash memory cell should be scaled down. In recent years, a technique of fabricating the flash memory cell by forming a floating gate and a control gate on a fin-type active region was proposed in order to scale down the gate. An example of this fin-type flash memory cell is disclosed in U.S. Pat. No. 6,657,252 to Fried et al.
FIG. 1 is a perspective view of the fin-type flash memory cell disclosed in U.S. Pat. No. 6,657,252. Referring to FIG. 1, a fin-type active region 100 is provided on a semiconductor substrate 99. An oxide layer pattern 102 is disposed on the fin-type active region 100, and a tunnel dielectric layer 110 is disposed on sidewalls 103 of the fin-type active region 100. Also, the tunnel dielectric layer 110 is covered with a floating gate 115, and the floating gate 115 is covered with an inter-gate dielectric layer 116. A control gate electrode 120 is also disposed on the inter-gate dielectric layer 116 to cross the fin-type active region 100.
The flash memory cell shown in FIG. 1 may improve the integration density of an electronic system, but the inter-gate dielectric layer 116 around the floating gate 115 may adversely affect the coupling ratio. In particular, as compared with a conventional planar gate type flash memory cell, the effective area of the tunnel dielectric layer 110 increases in the flash memory cell including the fin-type active region 100 as shown in FIG. 1, so that the amount of current passing between the floating gate 115 and a channel region may be greatly augmented. However, an increase in the effective area of the tunnel dielectric layer 110 leads to gains in the capacitance of the tunnel dielectric layer 110, but typically causes little variation in the capacitance of the inter-gate dielectric layer 116. As a result, the coupling ratio may be greatly reduced.